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[Multimedia program] VGA

Description: VGA 640x480 controller using FPGA Xilinx using Xilinx ISE 10
Platform: | Size: 1024 | Author: Odair | Hits:

[VHDL-FPGA-Verilog] edk_ctt

Description: fpga apu核嵌入式功能设计认证考试资料-fpga ise xilinx Low cost OEM and development Boards Customized Module Development
Platform: | Size: 1003520 | Author: nan | Hits:

[VHDL-FPGA-Verilog] Xilinx_DCM

Description: 基于ise 10.0来实现Xilinx的时钟设计和管理-Xilinx dcm digital clock manager
Platform: | Size: 8192 | Author: ise_dcm | Hits:

[VHDL-FPGA-Verilog] vvTutorialonXilinxISE10.1

Description: EGR426 W’09 Laboratory #1 Tutorial on Xilinx ISE 10.1-EGR426 W’09 Laboratory#1 Tutorial on Xilinx ISE 10.1
Platform: | Size: 1252352 | Author: lance | Hits:

[Linux-Unix] mgc_licen(1)

Description: license for ise12.2,最新而且很好用，请放心使用。-license for ise12.2，It s lastest fot ise 12.2,good ease to ues.
Platform: | Size: 387072 | Author: 邵磊 | Hits:

[VHDL-FPGA-Verilog] IS61WV51216BLL

Description: 备注：使用的是VeriLog HDL语言软件环境xilinx ISE 10.1，硬件：高教仪EXCD-1FPGA电路板。FPGA信号：spartan-3e . 功能编写硬件描述性语言实现FPGA对板上外设SRAM IS61WV51216BLL的读写，通过串口发送到上位机上，使用串口助手显示读取的数据。-Note: Use the VeriLog HDL language software environment xilinx ISE 10.1, hardware: Higher Miriam EXCD-1FPGA circuit boards. FPGA Signal: spartan-3e. Write functional hardware description language implementation of on-board peripherals SRAM IS61WV51216BLL FPGA to read and write, sent to the host computer through the serial port, use the serial Assistant displays the data read.
Platform: | Size: 5120 | Author: 李钿 | Hits:

[DSP program] OFDM_Security

Description: This a Simulink model that demonstrates an algorithm that applies wireless security on physical layer. The demonstration is based on 802.11a (simplified) and receiver is implemented on Xilinx Virtex 4 FPGA. The RAR file inlcudes 2 files: 1. Simulink model 2. initialization file. Software requirements: 1. Matlab, r2007a or later 2. Simulink with DSP and Comm blocksets 3. Xilinx ISE with System Generator for DSP 9.2i or later.
Platform: | Size: 160768 | Author: 徐滨 | Hits:

[VHDL-FPGA-Verilog] rax2

Description: rax2 fft implation the fft in verilog instance and in ise of xilinx it show how to istance fft core and the port used
Platform: | Size: 1024 | Author: LL | Hits:

[VHDL-FPGA-Verilog] Verilog-Design

Description: 包括三个文档: 1.基于Altera Quartus II 的模块化设计应用 2.基于Xilinx ISE的的模块化设计示例 3.模块化设计方法的设计流程-Consists of three documents: 1. Based on Altera Quartus II modular design applications 2. Xilinx ISE based on the modular design of Example 3. Modular Design for design process
Platform: | Size: 252928 | Author: Joseph | Hits:

[VHDL-FPGA-Verilog] XilinxFPGAISEDSPDESIGN(1-60)

Description: 系统讲述了XilinxFPGA的开发知识,包括FPGA开发简介、VerilogHDL语言基础、基于Xilinx芯片的HDL语言高级进阶、ISE开发环境使用指南、FPGA配置-System, the development of knowledge about XilinxFPGA, including the FPGA development profile, VerilogHDL language based on chip-based Xilinx HDL Language Advanced Advanced, ISE development environment, user guide, FPGA configuration ...
Platform: | Size: 11885568 | Author: 林方 | Hits:

[VHDL-FPGA-Verilog] SpiMaster

Description: This a verilog code for SPI Master testbench is also provided spi_top.v Xilinx ISE or Icarus verilog to compile and simulate-This is a verilog code for SPI Master testbench is also provided spi_top.v Xilinx ISE or Icarus verilog to compile and simulate
Platform: | Size: 9216 | Author: RutaliMulye | Hits:

[VHDL-FPGA-Verilog] lab_instructions1

Description: The objective of the labs today is to give you a basic understanding of FPGA design and enough experience to begin your own FPGA design with the ISE 10.1 tools and the Xilinx Spartan-3A DSP 1800A Starter Kit.-The objective of the labs today is to give you a basic understanding of FPGA design and enough experience to begin your own FPGA design with the ISE 10.1 tools and the Xilinx Spartan-3A DSP 1800A Starter Kit.
Platform: | Size: 1188864 | Author: Gopi | Hits:

[VHDL-FPGA-Verilog] lab_instructions2

Description: The objective of the labs today is to give you a basic understanding of FPGA design and enough experience to begin your own FPGA design with the ISE 10.1 tools and the Xilinx Spartan-3A DSP 1800A Starter Kit.-The objective of the labs today is to give you a basic understanding of FPGA design and enough experience to begin your own FPGA design with the ISE 10.1 tools and the Xilinx Spartan-3A DSP 1800A Starter Kit.
Platform: | Size: 2244608 | Author: Gopi | Hits:

[VHDL-FPGA-Verilog] lab_instructions3

Description: The objective of the labs today is to give you a basic understanding of FPGA design and enough experience to begin your own FPGA design with the ISE 10.1 tools and the Xilinx Spartan-3A DSP 1800A Starter Kit.-The objective of the labs today is to give you a basic understanding of FPGA design and enough experience to begin your own FPGA design with the ISE 10.1 tools and the Xilinx Spartan-3A DSP 1800A Starter Kit.
Platform: | Size: 1048576 | Author: Gopi | Hits:

[VHDL-FPGA-Verilog] Spartan-3ADSPs

Description: The objective of the labs today is to give you a basic understanding of FPGA design and enough experience to begin your own FPGA design with the ISE 10.1 tools and the Xilinx Spartan-3A DSP 1800A Starter Kit.-The objective of the labs today is to give you a basic understanding of FPGA design and enough experience to begin your own FPGA design with the ISE 10.1 tools and the Xilinx Spartan-3A DSP 1800A Starter Kit.
Platform: | Size: 1040384 | Author: Gopi | Hits:

[VHDL-FPGA-Verilog] XilinxISEDesignSuite12.1

Description: Xilinx ISE Design Suite 12.1 cd key
Platform: | Size: 1024 | Author: grs | Hits:

[VHDL-FPGA-Verilog] ise_book

Description: Xilinx公司推荐FPGA培训教材Xilinx ISE 9.xFPGA/CPLD设计指南的配套光盘内容，每个程序含verilog和VHDL两具版本-Training materials recommended by Xilinx Xilinx ISE 9.xFPGA/CPLD FPGA design guidelines supporting the CD content, each program contains two versions of verilog and VHDL
Platform: | Size: 8774656 | Author: 王建伟 | Hits:

[VHDL-FPGA-Verilog] finial_test

Description: 卷积码和Viterbi译码的源程序，在Xilinx ISE环境下使用Verilog编写，有助于卷积码和Viterbi译码的学习-Convolutional codes and Viterbi decoding of the source, in the Xilinx ISE environment, use of Verilog prepared to help convolutional codes and Viterbi decoding of the study
Platform: | Size: 5588992 | Author: lxz | Hits:

[VHDL-FPGA-Verilog] synth_fft

Description: fftprocessing can complete 256 pointsFFT.-Hardware Description Language(HDL)is an advanced electronic designmethod．After HDL was put into use，it has draw great attention and gained popularity．The design used Verilog HDL and Schematic for entry tools having good effect in the system design，Meanwhile，it adopted the core provided by Xilinx／nc. improving the design efficiency．The whole design which is implemented inXC2S600E device relied on ISE and advanced hierarchy design mind．Furthermore，it is simulated and verified．The frequency attains to 40.64MHz．this paper aims at demonstration the applying FPGA to FFT signal processing can complete 256 pointsFFT.
Platform: | Size: 56320 | Author: zzy | Hits:

[Software Engineering] dd

Description: 设计的随机数发生器可产生两个随机数，由一开关（RIN）进行控制，RIN为1时随机数发生器被清除，RIN为0时随机数发生器将产生1-6的两个随机数，可由LED数码管显示，显示的方式可由设计者自行设计，既可以选择数码管中的任两个LED显示随机数，也可让四位LED同时显示一个随机数（按一定的时间跳转显示）。根据给定的材料完成上述系统的设计，用Xilinx ise完成功能的设计与仿真，并最终下载到目标板XILINX SPARTAN-3 Starter Board上进行验证实现。-The random number generator can be designed by a random, produce two control switch (RIN), RIN is 1 random number generator is cleared, RIN is 0 random number generator will produce 1-6 two random, but by LED digital display, showing the way tube by designer to design, can choose the digital tube as two LED display random, also can let four leds also showed a random number (according to certain time jump displayed). According to the given material to complete the above system design, complete with the functional design of ise Xilinx with simulation, and finally downloaded to target Board SPARTAN- 3 Starter Xilinx Board test the realization.
Platform: | Size: 1631232 | Author: heyougen | Hits:

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